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5829
SERIAL DATA OUT SERIAL DATA IN HIGH-SIDE DRIVER REFERENCE
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
Intended primarily to drive high-current, dot matrix 9- and 24-wire printer solenoids, the UCN5829EB serial-input, latched sink driver provides a complete driver function with a minimum external parts count. Included on chip are constant-frequency PWM current control for each output driver, a user-defined output enable timeout, current sensing, and thermal shutdown. The 9-bit CMOS shift register and latches allow operation with most microprocessor/LSI-based systems. With a 5 V logic supply, these BiMOS devices will operate at data input rates greater than 3.3 MHz. The CMOS inputs cause minimum loading and are compatible with standard CMOS, PMOS, NMOS, and TTL circuits. A CMOS serial data output allows cascade connections in applications requiring additional drive lines as required for 24-wire printheads. The device features nine open-collector Darlington drivers, each rated at 50 V and 1.6 A. Current-control for each output is provided by an internal current-sensing resistor and a constant-frequency chopper circuit. An external high-side driver can be used to optimize print head performance. It is enabled by an on-chip driver during the output enable timeout. Internal logic sequencing prevents false output operation during power up. Other high-current devices for driving dot matrix printheads are the UDN2961B/W and UDN2962W. The UCN5829EB is supplied in a 44-lead power PLCC. Its batwing construction provides for maximum package power dissipation in a minimum-area, surface-mountable package.
42 STROBE SUPPLY 44 CLOCK RC EN RC C 41 RCV
9
Data Sheet 26185.50
IN
43
GND
7 8 9 10 11 12 13 14 15 16
ONE-SHOT
GND
17
NC
18
ABSOLUTE MAXIMUM RATINGS
Output Current Voltage, VOUT ............ 50 V Output Current, IOUT(S) (Continuous) ................................ 1.6 A (Peak) ............................................ 1.8 A Logic Supply Voltage, VDD .................. 7.0 V Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA .................................. -20C to +85C Junction Temperature, TJ ............... +150C* Storage Temperature Range, TS ............................... -55C to +150C
* Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. Caution: This CMOS device has input static protection but is susceptible to damage when exposed to extremely high static electrical charges.
T C UY DL ON RO PE DC EN UE IN ER TF NE OR CR IS O DF --
CURRENT CONTROL 39 38 37 36 35 34 33 32 31 GND SHIFT REGISTER LATCHES 30 29 GND NC
28 25 19 20 21 22 23 OUT 9 24 26 27 NO CONNECTION OUT 8 OUT 7 OUT 5 OUT 3 OUT 6 OUT 4 OUT 2 OUT 1
Dwg. PP-028A
V DD
CLK
NO CONNECTION
40
5
6
4
3
2
1
FEATURES
s s s s s s s s s s
1.6 A Continuous Output Current 50 V Minimum Sustaining Voltage Internal Current Sensing Constant-Frequency PWM Current Control Control for External High-Side Driver To 3.3 MHz Data Input Rate Low-Power CMOS Logic & Latches Internal Pull-Ups for TTL Compatibility User-Defined Output Enable Timeout Internal Thermal Shutdown Circuitry
Always order by complete part number: UCN5829EB .
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
FUNCTIONAL BLOCK DIAGRAM
+5 V 3 REN 4 C EN P.O.R. CHOP INHIBIT CURRENT LEVEL CONTROL 40 V REF 41 R CV = 5 k CLOCK SERIAL DATA IN 44 43
1%
HIGH-SIDE DRIVER 6 VDD ONE-SHOT
+5 V RC 5 CC
/2
STROBE 42
SHIFT REGISTER
26 OUT2
TO DRIVERS 1, 3, 5, 7, 9
LATCHES
TO DRIVERS 4, 6, 8
SQ R + - DRIVER TWO OF NINE DRIVERS <<1
SERIAL DATA OUT IN 9
1 2
7-17
29-39
Dwg. FP-015A
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
12.5
R J
T
/W C =6
10
7.5
5.0
2.5
R
JA
= 30 C/W
0 25 50 75 100 TEMPERATURE IN C 125 150
Dwg. GP-020B
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1991, 1995 Allegro MicroSystems, Inc.
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
TYPICAL INPUT CIRCUITS
VDD
TYPICAL OUTPUT DRIVER
OUTN
IN
<<1
Dwg. EP-021-2
Dwg. EP-010-3
ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V, in Test Circuit/Typical Application (unless otherwise noted).
Characteristic Symbol Test Conditions Min. Limits Typ. Max. Units
Output Power Drivers (OUT1 through OUT9 ) with VREF 4.5 V Output Leakage Current Output Saturation Voltage IOUT VOUT(SAT) VOUT = 50 V IOUT = 1.0 A IOUT = 1.6 A Output Sustaining Voltage Control Logic HSD Output Saturation Voltage Logic Input Voltage VCE(SAT) VIN(1) VIN(0) Logic Input Current IIN VIN = 5.0 V VIN = 0.8 V Reference Input Current Logic Supply Current (VREF = 2.0 V) Maximum Clock Frequency Serial Data Output Voltage IREF IDD VREF = 3.0 V All Drivers OFF All Drivers ON, No Load fclk VOUT(1) VOUT(0) Clock to Serial Data Out Delay Thermal Shutdown Temperature tPD TJ IOUT = -200 A IOUT = 200 A CL = 30 pF IC = 20 mA -- 3.5 -0.3 -- -- -- -- -- 3.3 4.5 -- -- -- 0.5 -- -- -- -90 500 15 55 5.0 4.7 250 -- 165 1.0 5.3 0.8 1.0 -180 900 25 75 -- -- -- 300 -- V V V A A A mA mA MHz V mV ns C VOUT(sus) IOUT = 1.6 A, L = 2.5 mH -- -- -- 50 1.0 1.0 1.5 -- 100 1.5 1.9 -- A V V V
Continued next page...
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V, in Test Circuit/Typical Application (unless otherwise noted).
Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units
Chopping Characteristics (TJ = +25C to +150C) with Fast Clamp Diodes Enable Timeout Chopping Frequency Duty Cycle Range Chop Current Level tEN fch dc ITRIP REN = 20 k, CEN = 0.01 F RC = 20 k, CC = 250 pF ton / ton + toff VREF = 2.0 V, fch < 100 kHz VREF = 2.8 V, fch < 100 kHz Output Current Control Range VREF ITRIP Delay Chop Inhibit Voltage Range td VREF ITRIP to IOUT(P), TA = +25C 190 90 15 0.9 1.26 1.0 0.5 -- 4.5 200 100 -- 1.0 1.4 -- -- 300 -- 210 110 < 50 1.1 1.54 3.2 1.6 500 VDD + 0.3 s kHz % A A V A ns V
Negative current is defined as coming out of (sourcing) the specified device terminal.
EXTERNAL HIGH-SIDE DRIVERS
NMOS
PMOS
CHARGE-PUMP CIRCUITRY FOR SINGLE-SUPPLY OPERATION
VBB
VBB + 10 V
VBB
VBB
0.022 F
10 V
Dwg. EP-028
Dwg. EP-027
Dwg. EP-026
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
TEST CIRCUIT AND TYPICAL APPLICATION
+36 V
CHARGE PUMP
POWER NMOS
LOADS (9)
V DD
OUTPUTS HIGH-SIDE DRIVER (HSD) V REF STROBE CLOCK SERIAL DATA IN GROUND R CV
20 k
+
20 F
0.01 F
RC C 250 pF RC EN IN 9 SERIAL DATA OUT
5 k 1%
Dwg. EP-023A
TRUTH TABLE
Serial Data Input H L X Clock Input Shift Register Contents* I1 I2 ... H R1 ... L R1 ... I9 R8 R8 Serial Data Output R7 R7 R8 X P8 H L R1 R2 ... R9 P1 P2 ... P9 P1 P2 ... P9 H H X H L Strobe Input Latch Contents* I1 I2 ... I9 Output Contents* I1 I2 ... I9 HSD OUTPUT
R1 R2 ... R9 XX...X P1 P2 ... P9
* Serial Data Output connected to Input9. L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
20 k
V DD
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
D
CLOCK A B
DATA IN E C STROBE F
G
HIGH-SIDE DRIVER OUT H LOAD CURRENT TO I OUT(asym) I OUT(P) td t on t off
Dwg. WP-011A
I TRIP
TIMING CONDITIONS
TA = +25C, Logic Levels are VDD and Ground
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ns D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ns E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 500 ns F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns G. Enable Timeout, tEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REN CEN H. Chop Period*, ton + toff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 RC CC
* Chopping is disabled if VREF is greater than 4.5 V.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
APPLICATIONS INFORMATION
The UCN5829EB is designed to drive high-current, 9- or 24-wire (3 devices cascaded) dot matrix impact printer solenoids. The internal CMOS control logic: 1) selects the operating channels from a 9- or 24-bit word previously loaded into the shift register, 2) controls the peak load current of the output drivers via nine constant-frequency switch-mode current choppers, 3) sets a user-defined print enable time, and 4) turns ON an external high-side driver during the print enable interval. Data present at the SERIAL DATA INPUT is transferred to the shift register on the low-to-high transition of the CLOCK input pulse. The data must appear at the input prior to the rising edge of the clock input waveform. On succeeding clock pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to its respective latch on the high-to-low transition of the STROBE (serial-to-parallel conversion). Drivers that have a logic high stored in their latch will be enabled for a set time interval (tEN) generated by an internal one-shot. The output current is internally sensed and controlled in a fixed-frequency chopper format. Between strobe pulses, a new data word can be clocked in for the next print enable cycle. PRINT ENABLE TIME A high-to-low transition of the STROBE input starts an internal one-shot which sets the print enable time (tEN) of the output drivers and the external high-side driver. The print enable time is determined by an external resistor (50 k max) and capacitor (100 pF min) at RCEN as tEN = REN CEN The print enable time can also be controlled from a microprocessor. In this mode, the internal one-shot is operated as an output disable function. In this mode, REN and CEN are not used; instead a 10 k series resistor is connected between RCEN and an externally generated output disable pulse. As before, on the high-to-low STROBE transition, the outputs will be enabled. They will remain enabled until a low-to-high logic (3.3 V) DISABLE transition at RCEN. When operating in a continuous chopping mode, and neither print enable timeout nor output disable are desired, RCEN should be grounded.
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
HIGH-SIDE DRIVER To reduce the current decay time at the end of a print enable cycle, an external high-side driver can be used and controlled by the HIGH-SIDE DRIVER (HSD) output. The HSD is designed to drive an external N-channel MOSFET (with accompanying charge pump circuitry). During the print enable time (tEN), the internal high-side driver is OFF, allowing the external high-side driver to be ON. If the external high-side driver is a P-channel device (eliminating the need for charge-pump circuitry), the HSD signal must be inverted for correct operation. If an external high-side driver is used, an external ground clamp diode is also required. OUTPUT CURRENT CONTROL Each of the nine channels consists of a power Darlington sink driver, internal low-value current-sensing resistor, comparator, and an R/S flip-flop. The output current is sensed and controlled independently in each channel by means of a fixed-frequency chopper which sets the flip-flop and allows the output to turn ON. As the current increases in the load it is sensed by the internal sense resistor until the sense voltage equals the trip voltage of the comparator. At this time, the flip-flop is reset and the output is turned OFF. Over the range of VREF = 1.0 V to 3.2 V, the output current trip point is a linear function of the reference voltage: ITRIP = VREF/2 To ensure an accurate chop current level, an external 5 k resistor (RCV) is used. The actual load current peak will be slightly higher than the trip point (especially for low-inductance loads) because of the internal logic and switching delays (typically 300 ns). After turnoff, the load current decays, circulating through the load and an external clamp diode. The output driver will stay OFF until the next chop pulse sets the flip-flop, turning ON the output, and allowing load current to rise again. The cycle repeats, maintaining the average printhead current at the desired level. The chop pulse frequency is determined by an external resistor and capacitor at RCC: fch = 1 2 R C CC
To reduce the power supply and ground noise developed when operating nine channels synchronously, the outputs are split into two groups (OUTPUTS 2, 4, 6, 8 and OUTPUTS 1, 3, 5, 7, 9) for chopping pulses.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
The chopping function is disabled when VREF > 4.5 V. To prevent operation at higher than allowable current levels, VREF should not exceed 3.2 V, except to disable the chopping function. DUTY CYCLE LIMITS For correct operation of the UCN5829EB, the duty cycle must be between 15% and 50% with 20% to 40% recommended. The lower limit is due to internal lockout circuitry while the upper limit guarantees synchronous operation. The duty cycle (dc) can be calculated as ton dc = ton + toff IOUT(P) / IOUT(asym) + vd / vc 1 + vd / v c
where IOUT(asym) = the asymptotic current value = vc/RL vd = discharge voltage across the load = VHSD + VDIODE vc = charge voltage across the load = VBB - VOUT(SAT) - VHSD For most practical cases, correct operation can be achieved if IOUT(asym) / IOUT(P) > 2.5. GENERAL For applications with 9-wire printheads, SERIAL DATA OUT should be connected to IN9. For 24-wire printhead applications, three devices (eight channels per device) are cascaded by connecting SERIAL DATA OUT to the next SERIAL DATA IN. Each of the CMOS logic inputs have internal pull-up resistors for TTL compatibility. An external transient-protection flyback diode is required at each output. Fast recovery diodes are recommended to reduce power dissipation in the UCN5829EB. Internal filtering prevents false triggering of the current sense comparator which can be caused by the recovery current spike of the diodes when the outputs turn ON. The SUPPLY terminal should be well decoupled with a capacitor placed as close as possible to the device. Internal power-ON reset circuitry prevents false output triggering during power up. Thermal protection circuitry is activated and turns OFF all drivers at a junction temperature of typically +165C. The thermal shutdown is independent of all other functions. It should not be used as another control input but is intended only to protect the chip from catastrophic failures due to excessive junction temperatures. The output drivers are re-enabled when the junction temperature cools down to approximately +145C.
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
TYPICAL APPLICATION Shown is a typical application with the UCN5829EB controlling a chop current of 1 A through a 3 mH, 9 load. To check the duty cycle and IOUT(asym)/IOUT(P) restrictions where vd = VHSD + VDIODE 1.5 + 1.5 = 3 vc = VBB - VOUT(SAT) - VHSD = 36 - 1.5 - 1.5 = 33 IOUT(asym) = vc / RL = 33 / 9 = 3.67 then IOUT(asym) / IOUT(P) = 3.67 / 1 = 3.67
The condition of IOUT(asym) / IOUT(P) > 2.5 is met and the duty cycle will be within the proscribed limits. The actual duty cycle is dc = IOUT(P) /IOUT(asym) + vd /vc 1 + vd /vc = 1.0/3.67 + 2.5/33 1 + 2.5/33 = 32%
For a 50 kHz chopping frequency and a 250 s print enable time, the remaining component values are with then and CC = 250 pF and CEN = 0.01 F RC = 1/(2 fch CC) = 1/(2 x 50 x 103 x 250 x 10-12) = 40 k REN = tEN / CEN = 250 x 10-6 / 10 x 10-9 = 25 k
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
Dimensions in Inches
(controlling dimensions)
28
18
29 0.319 0.291 0.021 0.013 0.695 0.685 0.656 0.650 0.319 0.291 0.050
BSC INDEX AREA
17
0.032 0.026
39
7
40 0.020
MIN
44
1
2
6
0.656 0.650 0.695 0.685
Dwg. MA-005-44A in
0.180 0.165
NOTES: 1. Webbed lead frame. Leads 7 through 17 and 29 through 39 are internally one piece. 2. Exact body and lead configuration at vendor's option within limits shown. 3. Lead spacing tolerance is non-cumulative.
5829
9-BIT SERIAL-INPUT, LATCHED SINK DRIVER
Dimensions in Millimeters
(for reference only)
28
18
29 8.10 7.39 0.533 0.331 17.65 17.40 16.662 16.510
INDEX AREA
17
0.812 0.661
8.10 7.39 1.27
BSC
39
7
40 0.51
MIN
44
1
2
6
4.57 4.20
16.662 16.510 17.65 17.40
Dwg. MA-005-44A mm
NOTES: 1. Webbed lead frame. Leads 7 through 17 and 29 through 39 are internally one piece. 2. Exact body and lead configuration at vendor's option within limits shown. 3. Lead spacing tolerance is non-cumulative.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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